1. Related Field
The disclosed methods and systems relates to a phase-change random access memory device, and more particularly to a phase-change random access memory device with a reduced layout area.
This application claims priority from Korean Patent Application No. 10-2006-0020654 filed on Mar. 3, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Phase-change random access memories (PRAMs) store data using a phase-change material, such as any number of chalcogenide alloys, capable of taking either a crystalline state or an amorphous state based on specific applications of heating and cooling. The resistance of a crystalline phase-change material is relatively low compared to the resistance of the amorphous phase-change material. The crystalline state is referred to as a set (or “0”) state, and the amorphous state is referred to as a reset (or “1”) state.
FIG. 1 is a circuit diagram of a conventional phase-change random access memory (PRAM) device 1. As shown in FIG. 1, the conventional PRAM device 1 includes a plurality of memory blocks (BLKk; k=0˜n), a plurality of main word lines (MWLp; p=0˜m), a plurality of local word lines (LWLk; k=0˜n) and a plurality of section word line drivers (SWDk; k=0˜n).
The plurality of section word line drivers (SWDk; k=0˜n) are arranged between each of the plurality of memory blocks (BLKk; k=0˜n). The section word line drivers (SWDk; k=0˜n) adjust the voltage levels of the plurality of local word lines (LWLk; k=0˜n) in response to voltages applied to the respective main word lines (MWLp; p=0˜m). As shown in FIG. 1, the plurality of section word line drivers (SWDk; k=0˜n) are comprised of inverters having of PMOS transistors 10 pulling-up the voltage levels of the plurality of local word lines (LWLk; k=0˜n) and NMOS transistors 20 pulling-down device the voltage levels of the plurality of local word lines (LWLk; k=0˜n).
Since the conventional section word line drivers (SWDk; k=0˜n) use inverters in such a manner, its layout area can be considerably large. That is, since it is desirable to use PMOS transistors 10 and NMOS transistors 20 arranged together, an isolation area (as required under relevant design rules) must be provided between each of the PMOS transistors 10 and NMOS transistors 20 to reduce the possibility of latch-up. In addition, since the PMOS transistors 10 occupy a much greater area than the NMOS transistors 20, it is necessary to reduce the number of PMOS transistors 10 used in product design to avoid an increase of the layout area.